Generally, a plurality of devices/components (e.g., transistors, diodes, etc.) may be designed and embedded into an IC chip/die, which then may be placed into a package (e.g., plastic casing) or used as a bare die for placement onto a printed circuit board (PCB) of an electronic device. In addition to traditional technology node scaling at the transistor level, three-dimensional (3D) IC chip stacking is increasingly being utilized to continue the use of current semiconductor manufacturing technologies (e.g., 28 nm, 22 nm, etc.) to create 3D system-on-chip (SoC) devices and provide solutions for meeting performance, power, and bandwidth requirements of various electronic devices. A 3D SoC device may include several logic, memory, analog, or other chips of different technology nodes that may be connected to each other by using TSV architecture. Typically, TSVs are vertical vias etched into a silicon layer and filled with a conductive material (e.g., copper (Cu)), to provide connectivity for transferring electronic signals or power supplies between the vertically stacked IC chips or between an IC chip and an IC package substrate.
FIG. 1 schematically illustrates an example IC chip stack structure including a face-to-face (F2F) bonding of IC chips. As illustrated, the 3D IC chip stack includes IC chips 101 and 103 with TSVs 105 used to interconnect the 3D stack (e.g., IC chip 101), through an interconnection layer 107 (e.g., including solder balls, copper pillars, micro-bumps) to an IC package substrate 109. The IC package substrate 109 may include an interconnection layer 111 (e.g., including a solder ball grid array) for connecting to another substrate or a printed circuit board of an electronic device. As illustrated, the IC chips may include back-end-of-line (BEOL) metal layers including front metal layers 113 and a back metal layer 115, a device layer 117, and a silicon layer/IC substrate 119. Also, the device layer 117 may include one or more dielectric layers for providing isolation between the devices. The F2F bonding of the IC chips 101 and 103 may be through metal vias connected to a final metal layer included in the front metal layers 113.
In a 3D SoC device, individual SoC functional blocks may be partitioned onto individual IC chips for connection during 3D IC packaging, where shorter wire lengths in the 3D configuration allow for performance gains and a decrease in overall power consumption of the device. Also, reduction in wire lengths reduces total number of BEOL metal layers needed. In a homogeneous application of a 3D SoC device, functional blocks within a single technology node are partitioned resulting in a smaller die/chip size on Si wafers for increased yield and device-per-wafer efficiency. Such an application may allow for extension of existing technology for further manufacturing on currently available/purchased manufacturing toolsets resulting in extension of 14 nm technology node and delaying a need for a reduction (e.g., 10 nm scaling) in the technology node. In a heterogeneous application of a 3D SoC device, the block partitioning may be targeted based on scalability, wherein higher scalable digital cores and IP are scaled to advanced technology nodes. Devices that may not scale well, such as SRAM, I/O's, and other analog devices may be manufactured on older technology. Such an application may result in higher overall yield and reduced cost due to the possibility of using older technology for part of the system.
As noted, a 3D SoC device/IC chip stack may be formed by F2F bonding of vertically aligned semiconductor wafers that include an array of IC chips on each wafer, where bonded 3D IC chips may be separated from each other through dicing lanes between adjacent bonded 3D IC chips. A current industry approach for 3D SoC devices includes wafer bonding in a F2F configuration, where TSVs are etched into one of the wafers (e.g., bottom wafer) after the bonding is completed (TSV-last approach). However, a TSV-last approach requires sophisticated alignment, design and process techniques. Also, the TSV structures and quality in a 3D SoC device using a TSV-last approach may be negatively impacted as etching of a TSV from the backside of an IC substrate may be difficult, e.g., causing a “blowout” when reaching the TSV contact point.
A need therefore exists for a methodology enabling integration of TSVs in a 3D SoC device prior to BEOL processes.